Education
Academic background
Bachelor's Degree in Computer Engineering
2021 - 2024
Università di Catania - Catania, Italy
Master's Degree in Computer Engineering Embedded System
2024 - Current
Politecnico di Torino - Turin, Italy
Portfolio
A collection of my university projects and work
P4-Adder
Academic Year 2024/2025
Developed the P4-adder with particular attention to the sparse tree carry generator.
Intercept and SSE calculator on hardware
Academic Year 2024/2025
FSM-based machine to compute intercept given the slope, another FSM-based machine to compute the Sum Squared Error.
QEMU Modding (OS)
Academic Year 2024/2025
Modified QEMU to allow the emulation of a new implemented board NXP S32k3x8, and to emulate some of the peripheral
QEMU Modding (Cybersecurity)
Academic Year 2024/2025
Added the TPM as a new usable peripheral on QEMU, using OpenSSL library to emulate cryptographic operation. Build the TPM 2.0 from scratch.
Custom Optimizer for gate-level netlist
Academic Year 2024/2025
Developed a custom power optimizer in TCL for gate-level netlists. The tool optimizes power consumption by selectively adjusting the voltage threshold of cells while adhering to design constraints.
DLX processor
Academic Year 2024/2025
Implementend a processor with DLX architecture pipelined in VHDL.
UVM testbench
Academic Year 2024/2025
Developed a UVM testbench, written in SystemVerilog, to run in QuestaSIM, to test P4 adder and a FSM CU.